The MOS 65xx series has a 256-byte range of low memory referred to as zero page. Memory stored in this region is significantly faster to access and modify.
Like all modern compilers, LLVM assumes generally that the target machine has a large number of target registers that are more or less interchangeable. This restriction is loosened, at some cost to code complexity, for the X86 targets, but generally most targets assume that you have a range of compiler-controllable registers.
Because "virtual registers" has another predefined meaning in LLVM land, we use the term imaginary register to refer to a byte in zero page memory. It's represented at codegen time by a symbol like __rc17 or __rs5, which is then translated to an actual memory address by the linker at link time.
The number of imaginary registers is user-selectable. To decide how many registers LLVM-MOS should use, use the --num-zp-regs=64 flag to clang, replacing 64 with the number of usable zero page locations. clang will only emit references to imaginary registers in the range from __rc0 to __rc[N-1]. This is how LLVM-MOS can be made to generate optimal output for very different 65xx architectures.
LLVM-MOS does not assume that imaginary registers need to be consecutive! Many targets have non-consecutive usable zero page memory locations.